Accession Number : AD0163672

Title :   FIFO Shift Register Memory with Marker and Data Bit Storage.

Descriptive Note : Patent,

Corporate Author : OFFICE OF THE SECRETARY OF THE ARMY WASHINGTON D C

Personal Author(s) : Fagen,Lloyd D. ; Hadden,David R. , Jr. ; Haratz,David ; Sario,Lorenz M.

Report Date : 29 FEB 1972

Pagination or Media Count : 7

Abstract : The patent describes a first-in, first-out (FIFO) memory having a plurality of memory cells, each for storing one data bit and one marker bit. The marker bit is provided for steering the data bits into successive memory cells when writing. Reading data is accomplished by shifting the data in succession out one end of the FIFO. Each memory cell consists only of MOS-transistors, which are connected so as to function as sample-and-hold devices and clocked inverter devices. One sample-and-hold transistor and one inverter each connected to the same clock will store a bit, either data or marker. Sample-and-hold transistors and inverters are coupled between the bit storage sections of common and adjacent memory cells so as to provide the proper logic for steering the data bits for shifting to adjacent cells the data and marker bits.

Descriptors :   (*DATA STORAGE SYSTEMS, *PATENTS), (*SHIFT REGISTERS, PATENTS), MEMORY DEVICES, LOGIC CIRCUITS, TRANSISTORS

Distribution Statement : APPROVED FOR PUBLIC RELEASE