Accession Number : AD0488968

Title :   REDUNDANCY IN THRESHOLD LOGIC NETWORKS.

Descriptive Note : Technical rept.,

Corporate Author : TEXAS UNIV AT AUSTIN LABS FOR ELECTRONICS AND RELATED SCIENCE RESEARCH

Personal Author(s) : Bargainer, James Daniel, Jr. ; Coates, Clarence L.

Report Date : 01 AUG 1966

Pagination or Media Count : 97

Abstract : In this paper, methods are presented for designing error correcting capabilities into threshold gate networks so that the logic gates themselves correct errors of the system. A method is first presented which is based on the tree method of Coates and Lewis for the realization of threshold gate networks. In this method, the error correcting network is designed from the Boolean function to be realized. A primary realization is a realization for some function on the tree such that either the separating function or the gaps are assigned without knowledge of any other realizations on the tree. It is shown that a realization obtained by the tree method will correct errors of gates in the system if and only if all primary realizations are selected so that they will correct errors of gates in the primary realization. Relations are than presented for selecting the primary realizations. In the second part of this paper, three methods are presented for adding redundancy to a given realization so that errors of gates are corrected by the level of logic immediately following the occurrence of the error. In the final section, it is shown that correcting errors in the logic gates, themselves, requires fewer levels of logic and, for many relizations, fewer gates than when majority gates are used to correct the errors.

Descriptors :   *REDUNDANT COMPONENTS), (*GATES(CIRCUITS), MATHEMATICAL PREDICTION, THEORY, ERRORS, TOPOLOGY, LINEAR PROGRAMMING, RELIABILITY(ELECTRONICS), MATHEMATICAL ANALYSIS.

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE