
Accession Number : AD0489334
Title : A STUDY OF HAZARDS IN THRESHOLD NETWORKS.
Descriptive Note : Technical rept.,
Corporate Author : TEXAS UNIV AT AUSTIN LABS FOR ELECTRONICS AND RELATED SCIENCE RESEARCH
Personal Author(s) : Howe, Alfred Bart ; Coates, Clarence L.
Report Date : 05 AUG 1966
Pagination or Media Count : 113
Abstract : This paper is concerned with the study of logic hazards in threshold gate networks. Eichelberger has proved that logic hazards are not present in a sumofproduct (productofsum) realization which realizes all of the possible 1(0) prime implicants of the given Boolean function. Logic gates of the AND or NOR (OR or NAND) variety realize single 1(0) prime implicante, therefore, a gate is required for each 1(0) prime implicant to be realized and the problem of eliminating logic hazards is straightforward. A single threshold gate, however, realizes a number of prime implicants. Moreover, the number of prime implicants realized by a network that incorporates more than a single threshold gate is not uniquely determined either by the Boolean function being realized or by the number of gates involved. As a result, it is often possible to control the prime implicants and hence the hazards without increasing the number of gates required. A method is first presented for determining if a given threshold realization contains any logic hazards within a particular prime implicant. (Author)
Descriptors : (*GATES(CIRCUITS), RESPONSE), HAZARDS, SPECIAL FUNCTIONS(MATHEMATICAL).
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE