Accession Number : AD0666735
Title : SYNTHESIS AND MINIMIZATION OF DIAGRAMS WITH REAL LOGICAL ELEMENTS OF THE TYPE AND-NOT OR OR-NOT,
Corporate Author : FOREIGN TECHNOLOGY DIV WRIGHT-PATTERSON AFB OHIO
Personal Author(s) : Yakubaitis,E. A. ; Shmaukstel,N. P.
Report Date : 10 AUG 1967
Pagination or Media Count : 10
Abstract : By real logical elements is meant elements which have a time of operation which is not equal to zero. In the making of diagrams that are not constructed on such elements, at the time of transitions from cycle to cycle there may occur contests leading sometimes to errors in the working of the diagram. To the contests which arise in some transitions there corresponds in the logical formula, which describes the working of the diagram, the disjunction or conjunction of two or more terms whose value at least for one in this transition changes from 0 to 1 and for at least one from 1 to 0. With the presence of such terms the contests are termed hazardous. In this article there is provided a method for the synthesis of the diagrams on real AND-NOT or OR-NOT, which is based on the use of the same algorithms.
Descriptors : (*LOGIC CIRCUITS, ALGEBRAS), ERRORS, TIME, SWITCHING CIRCUITS, ALGORITHMS, SPECIAL FUNCTIONS(MATHEMATICAL), OPTIMIZATION, SYNTHESIS, USSR
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE