Accession Number : AD0675925

Title :   CALCULATION OF STEADY-STATE ERRORS IN DIGITAL-TO-ANALOGUE LADDER CONVERTORS,

Corporate Author : BRITISH COLUMBIA UNIV VANCOUVER DEPT OF ELECTRICAL ENGINEERING

Personal Author(s) : Donaldson,R. W. ; Chan,D.

Report Date : 07 APR 1967

Pagination or Media Count : 2

Abstract : A method for calculating least upper bounds on the magnitude and variance of the steady-state analogue voltage error in digital-to-analogue ladder convertors is presented. Tight bounds on the magnitude and variance of the error are calculated as a function of resistor tolerance, steady-state voltage source error and number of bits decoded. (Author)

Descriptors :   (*DIGITAL TO ANALOG CONVERTERS, ERRORS), FIXED RESISTORS, VOLTAGE, MATHEMATICAL ANALYSIS, CANADA

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE