Accession Number : AD0707691

Title :   A STUDY OF DIGITAL NETWORK STRUCTURE AND ITS RELATION TO FAULT DIAGNOSIS.

Descriptive Note : Doctoral thesis,

Corporate Author : ILLINOIS UNIV URBANA COORDINATED SCIENCE LAB

Personal Author(s) : Hayes,John Patrick

Report Date : MAY 1970

Pagination or Media Count : 142

Abstract : A network model, is introduced for the study of fault diagnosis in digital logic networks. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network can be obtained. The use of this model greatly simplifies fault analysis and test generation. The structure of the classes of indistinguishable faults in normal NAND networks is studied. It is shown that for certain types of networks, the indistinguishability classes can be characterized in a very simple manner. The conditions under which masking can occur are examined. These conditions lead to efficient methods for generating multiple-fault detection test sets. Some general bounds for the number of tests required by a network are examined. It is proven that for a n-input fanout-free network, the cardinality of any minimal detection or location test set lies between 2(square root of n) and 2n. It is argued that a 2-level realization of a random n-variable function requires, on the average, 2 to the (n-1) power tests to detect all faults. It is shown that for certain classes of functions there exists multi-level realizations which require relatively few tests, and for which complete detection test sets can easily be generated. (Author)

Descriptors :   (*SWITCHING CIRCUITS, RELIABILITY(ELECTRONICS)), (*LOGIC CIRCUITS, MAINTENANCE), FAILURE(ELECTRONICS), COMPUTER LOGIC, NETWORKS, THESES

Subject Categories : Computer Systems

Distribution Statement : APPROVED FOR PUBLIC RELEASE