Accession Number : AD0711306

Title :   A PARALLEL BCH DECODER.

Descriptive Note : Technical rept.,

Corporate Author : MONTANA STATE UNIV BOZEMAN ELECTRONICS RESEARCH LAB

Personal Author(s) : Laws,Ben A. , Jr

Report Date : 15 JUN 1970

Pagination or Media Count : 221

Abstract : The subject of this technical report is the detailed design of a special purpose digital computer to decode the BCH codes. Report content may be summarized as follows. A review of the BCH decoding algorithms and decoders is made, including the applicable microcellular and macrocellular techniques. The BCH decoding algorithms are discussed and organized for execution by a parallel processor. All algorithms are implemented as APL programs to verify their operation. A detailed design for a parallel processor is described. Also included are discussions of fault detection and correction, operation for different code word lengths, an operation for different number of errors. The logic design of the parallel processor is simulated in detail by an assembly language program. Finally, a recommendation is made for further research in the areas of parallel processor and algorithm design. (Author)

Descriptors :   (*DECODING, ALGORITHMS), (*COMPUTERS, DESIGN), CODING, ERRORS, PROBABILITY, MATRICES(MATHEMATICS), DIGITAL COMPUTERS, COMPUTER PROGRAMS, SIMULATION

Subject Categories : Computer Programming and Software
      Computer Hardware
      Cybernetics

Distribution Statement : APPROVED FOR PUBLIC RELEASE