Accession Number : AD0714511

Title :   Enhancing Testability of Large-Scale Integrated Circuits Via Test Points and Additional Logic.

Descriptive Note : Technical rept.,

Corporate Author : STANFORD UNIV CALIF STANFORD ELECTRONICS LABS

Personal Author(s) : Williams,Michael J. Y.

Report Date : SEP 1970

Pagination or Media Count : 71

Abstract : The work studies methods of using test points in conjunction with additional logic gates to provide an easy means to set or check the state. Among several logic modification schemes, the most useful appears to be one in which a single test point can be used to switch the circuit into a second mode of operation, a 'test mode'. In the test mode the flip-flops are reconnected to form a shift register, so that the state can be easily set or checked: however it is not possible to guarantee correct operation in this mode in the presence of a fault. After an initial state has been set, the circuit can be switched to normal mode for a test, then returned to the test mode so that the final state can be checked. For a synchronous sequential circuit whose state can be easily set or checked, the problem of generating a test to detect a given logical fault reduces to the problem of generating a test for the fault in a purely combinational network of similar complexity. The cost of such circuit modifications was analyzed. (Author)

Descriptors :   (*INTEGRATED CIRCUITS, *NONDESTRUCTIVE TESTING), CIRCUIT TESTERS, RELIABILITY(ELECTRONICS), COST EFFECTIVENESS, TEST METHODS

Subject Categories : Electrical and Electronic Equipment
      Test Facilities, Equipment and Methods

Distribution Statement : APPROVED FOR PUBLIC RELEASE