Accession Number : AD0720330
Title : Derivation of Minimum Test Sets for Unate Logical Circuits.
Descriptive Note : Technical note,
Corporate Author : STANFORD UNIV CA STANFORD ELECTRONICS LABS
Personal Author(s) : Betancourt, Rodolfo
Report Date : AUG 1970
Pagination or Media Count : 27
Abstract : A derivation of tests sets S sub 0 and S sub 1 for irredundant unate logical circuits is presented. It is shown that these sets (S sub 0 and S sub 1, respectively) detect all stuck-at-0 and stuck-at-1 faults in all realizations with no internal inverters of a given unate function. They can be obtained easily from the minimum sum and minimum product forms, from a Karnaugh map or from a Hasse diagram of the function. These sets are minimum in the sense that there is no set with a smaller number of elements that detects all faults in the class of realizations of a logical function. In particular, it is found that a two-level AND-OR (OR-AND) network needs all the tests in S sub 0 (S sub 1). (Author)
Descriptors : *LOGIC CIRCUITS, RELIABILITY(ELECTRONICS), COMPUTER LOGIC, GATES(CIRCUITS), SET THEORY, TEST METHODS.
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE