Accession Number : AD0736519

Title :   On Round-Off Error of Floating-Point Addition with Guard Digits,

Corporate Author : PRINCETON UNIV N J DEPT OF ELECTRICAL ENGINEERING

Personal Author(s) : Kaneko,Toyahisa ; Liu,Bede

Report Date : 1971

Pagination or Media Count : 5

Abstract : The assumption of double precision binary arithmetic operation is often made in the analysis of the finite word effect on digital signal processors. Some recent computers, such as those in the IBM 360 series, use radix 16 and single precision with guard digit in floating-point addition. In this paper, a bound on the round-off error for floating-point addition in single precision with guard digits is derived. Comparison with double precision addition is made. (Author)

Descriptors :   (*COMPUTER PROGRAMMING, *BINARY ARITHMETIC), ERRORS, ACCURACY, DIGITAL COMPUTERS

Subject Categories : Theoretical Mathematics
      Computer Programming and Software
      Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE