Accession Number : AD0736827
Title : Digital Logic Simulator.
Descriptive Note : Master's thesis,
Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OHIO SCHOOL OF ENGINEERING
Personal Author(s) : Niederhauser,John R.
Report Date : DEC 1971
Pagination or Media Count : 160
Abstract : Digital Logic Simulator (DLS) is a CDC 6600 computer program which simulates synchronous and asynchronous networks of digital logic elements. It is used at Air Force Institute of Technology to verify digital logic designs. DLS uses a state variable model which associates time delays with all elements. Thus, the effects of propagation delays on circuit behavior can be analyzed. DLS has four operation modes which allow the user to test circuits at various levels of complexity. A complete users manual is included in the thesis which describes the detailed features, capabilities, and language specifications for DLS. (Author)
Descriptors : (*LOGIC CIRCUITS, SIMULATION), (*COMPUTER PROGRAMS, INSTRUCTION MANUALS), TEST METHODS, PROGRAMMING LANGUAGES, DIGITAL COMPUTERS, THESES
Subject Categories : Computer Programming and Software
Distribution Statement : APPROVED FOR PUBLIC RELEASE