Accession Number : AD0736895

Title :   A Parallel Arithmetic Unit,

Corporate Author : FOREIGN TECHNOLOGY DIV WRIGHT-PATTERSON AFB OHIO

Personal Author(s) : Avaev,A. V. ; Vizun,I. D. ; Golovina,M. A. ; Laut,V. N. ; Sokolov,A. A.

Report Date : 04 NOV 1972

Pagination or Media Count : 8

Abstract : A parallel arithmetic unit for digital computers is fitted with two pairs of registers, each divided into a digit sum register and a digit transfer register. Each register has on its input AN and GATE which lies in a feedback circuit to input elements of the register in the other pair, AN and GATE to carry out the logic operations, and a three input adder. The clear signals are passed to each and GATE and adder through control wires. (Author)

Descriptors :   (*DIGITAL COMPUTERS, *PATENTS), LOGIC CIRCUITS, SHIFT REGISTERS, USSR

Subject Categories : Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE