
Accession Number : AD0745720
Title : Easily Testable Realizations for Logic Functions.
Descriptive Note : Technical rept.,
Corporate Author : IOWA UNIV IOWA CITY DEPT OF MATHEMATICS
Personal Author(s) : Reddy,Sudhakar M.
Report Date : MAY 1972
Pagination or Media Count : 35
Abstract : Several techniques to realize networks for nvariable logic functions are given such that the fault detecting sets (under the assumption that single gates are faulty) have (n+4) members and also these fault detecting sets are independent of the function being realized. These networks use two input Exclusive OR gates and AND gates. Techniques to design networks with devices realizing minput even parity functions and AND gates are also given which require fault detecting test sets, that are independent of the function being realized, with (n + (2 to the mth power)) members. Techniques to design the checker and the network to generate the test sets are also given. (Author)
Descriptors : (*DIGITAL COMPUTERS, *RELIABILITY(ELECTRONICS)), (*GATES(CIRCUITS), DESIGN), (*LOGIC CIRCUITS, MAINTENANCE), MATHEMATICAL LOGIC, COMPUTER LOGIC, TEST SETS, SPECIAL FUNCTIONS(MATHEMATICAL), REDUNDANT COMPONENTS, THEOREMS
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE