Accession Number : AD0753819
Title : Some Contributions to Redundancy Theory.
Descriptive Note : Technical rept.,
Corporate Author : IOWA UNIV IOWA CITY DEPT OF MATHEMATICS
Personal Author(s) : Pradhan,Dhiraj K.
Report Date : NOV 1972
Pagination or Media Count : 152
Abstract : So far it has been thought that there do not exist efficient codes suitable for error control in bit wise logical computations. This was basically due to certain negative results established by previous researchers. In this thesis this problem is investigated in a new framework. A crucial assumption that led to the negative results established in a new framework. A crucial assumption that led to the negative results is found unnecessary and hence discarded. Then a class of codes is exhibited and shown to be useful for error control. Furthermore it is shown that the efficiency of the proposed scheme is asymptotically optimum and also far better than the earlier known scheme. The usefulness of this technique is then extended to the design of fault-tolerant arithmetic processors. There has been extensive work done toward the design of fault-tolerant combinational logic networks. A new formulation is given to this problem and several results are established which identify the equivalence in redundancies of fault-tolerant realizations and hazard-free realizations. (Author)
Descriptors : (*DIGITAL COMPUTERS, *REDUNDANT COMPONENTS), (*LOGIC CIRCUITS, RELIABILITY(ELECTRONICS)), SWITCHING CIRCUITS, CODING, ERRORS, CONTROL SYSTEMS, MATRICES(MATHEMATICS), MATHEMATICAL LOGIC, MATHEMATICAL MODELS, THEOREMS, THESES
Subject Categories : Computer Hardware
Mfg & Industrial Eng & Control of Product Sys
Distribution Statement : APPROVED FOR PUBLIC RELEASE