Accession Number : AD0758165
Title : Multiple Faults in Combinational Logic.
Descriptive Note : Technical rept.,
Corporate Author : AUBURN UNIV ALA DIGITAL SYSTEMS LAB
Personal Author(s) : Shah,H. G. ; Carroll,B. D. ; Jones,D. M.
Report Date : MAR 1973
Pagination or Media Count : 72
Abstract : The problem of multiple fault detection in combinational logic network is addressed. A number of test set generation procedures are discussed. A couple of methods to reduce number of faults to be considered in test generation procedures are also discussed. The later approaches study topological aspects of networks. An EXCLUSIVE-OR method is developed which yields a general Boolean expression implying the complete test set for any specified multiple fault. This method is compared with other similar approaches appearing in recent literature. (Author)
Descriptors : (*LOGIC CIRCUITS, MAINTENANCE), (*RELIABILITY(ELECTRONICS), MATHEMATICAL PREDICTION), TEST METHODS, MULTIPLE OPERATION, COMPUTER LOGIC, GATES(CIRCUITS), FAILURE(ELECTRONICS)
Subject Categories : Mfg & Industrial Eng & Control of Product Sys
Distribution Statement : APPROVED FOR PUBLIC RELEASE