Accession Number : AD0768804
Title : On Generating Near Minimum Test Sets.
Descriptive Note : Technical rept.,
Corporate Author : AUBURN UNIV ALA DEPT OF ELECTRICAL ENGINEERING
Personal Author(s) : Ellis,John T. ; Carroll,B. D.
Report Date : 31 AUG 1973
Pagination or Media Count : 88
Abstract : A computerized algorithm for generating near minimum test sets for fault detection in combinational logic circuits is presented. The advantages of the approach in this algorithm over classical techniques are shown. The algorithm is then described and illustrated in great detail. Two software implementations of the algorithm are also given. Finally, comparisons and contrasts between this algorithm and other similar ones are described. (Author)
Descriptors : (*COMPUTER PROGRAMMING, ALGORITHMS), (*LOGIC CIRCUITS, TEST SETS), COMPUTER PROGRAMS, MATHEMATICAL LOGIC, GATES(CIRCUITS), INSTRUCTION MANUALS
Subject Categories : Electrical and Electronic Equipment
Computer Programming and Software
Distribution Statement : APPROVED FOR PUBLIC RELEASE