Accession Number : AD0804037

Title :   DESIGN OF THE G-21 MULTI-PROCESSOR SYSTEM,

Corporate Author : CARNEGIE INST OF TECH PITTSBURGH PA

Personal Author(s) : Quatse, Jesse T.

Report Date : 26 FEB 1965

Pagination or Media Count : 35

Abstract : During the summer of 1963, a multi-processor version of the CDC G-20 (the G-21) was developed for the Computation Center of Carnegie Institute of Technology. The purpose was to double the memory capacity and processing speed of the existing G-20 system. Since then, the system has continued to evolve as the needs of the Computation Center continue to grow. The purpose of this paper is to describe the memory control electronics which underlie memory time-sharing. The important related engineering problems are discussed in the terms of the current G-21 system. (Author)

Descriptors :   *TIME SHARING), (*COMPUTER PROGRAMMING, (*DATA STORAGE SYSTEMS, DIAGRAMS), (*MEMORY DEVICES, MODULES(ELECTRONICS)), DISPLAY SYSTEMS, DATA PROCESSING, COMPUTER PROGRAMMING, SYNCHRONIZATION(ELECTRONICS), CONTROL SEQUENCES, RELAXATION OSCILLATORS.

Subject Categories : Computer Programming and Software
      Computer Hardware
      Computer Systems

Distribution Statement : APPROVED FOR PUBLIC RELEASE