Accession Number : AD0859160

Title :   Burn-In Screening Techniques for Integrated Circuits.

Descriptive Note : Final rept. 5 Apr 68-5 Apr 69,

Corporate Author : BOEING AEROSPACE CO SEATTLE WA

Personal Author(s) : Brown, Robert W. ; Ainsworth, Walter W. ; Read, John C. ; Hamilton, Arnold E.

Report Date : AUG 1969

Pagination or Media Count : 291

Abstract : The final report presents the results of a program to study burn-in screening techniques for integrated circuits. A comprehensive guide to the specification of optimized burn-in screening for high-reliability integrated circuits is presented. The background material and data necessary to select an optimized burn-in screen are presented and the trades which must be made are discussed. The material included was obtained by survey and a laboratory test program. The report is divided into four sections: Section I is an introduction; Section II includes background material necessary to select and specify burn-in screening techniques and relates screening methods to specific defects in tabular form; Section III presents an economic study of burn-in screening methods and limit stress testing; Section IV describes the laboratory test program and results. The detailed results of an industry survey comprising the opinion of nineteen integrated circuit users and eleven manufacturers related to failure predominance, burn-in techniques and cost are included in the appendices. (Author)

Descriptors :   (*INTEGRATED CIRCUITS, NONDESTRUCTIVE TESTING), RELIABILITY(ELECTRONICS), FAILURE(ELECTRONICS), DIGITAL SYSTEMS, GATES(CIRCUITS), LOGIC CIRCUITS, SEMICONDUCTORS, QUESTIONNAIRES, BONDING, STRESSES, COSTS.

Subject Categories : Electrical and Electronic Equipment
      Test Facilities, Equipment and Methods

Distribution Statement : APPROVED FOR PUBLIC RELEASE