Accession Number : AD0886467
Title : Modeling of Logical Schemes on a Digital Computer,
Corporate Author : FOREIGN TECHNOLOGY DIV WRIGHT-PATTERSON AFB OH
Personal Author(s) : Boyanov, K. ; Velichkov, T.
Report Date : 06 JAN 1971
Pagination or Media Count : 11
Abstract : Known methods for the modeling and analysis of logical circuits either neglect the delay time within the individual elements or consider two types of elements with and without fixed delays. The presently described model allows the tracing of the states of logical circuits without limitation on the delay time within component elements. Experimental error-search in standard adders and registers by means of induced incorrect couplings and delays points to the feasibility of standard subprograms for the analysis and diagnostics of different logical schemes. (Author)
Descriptors : (*LOGIC CIRCUITS, MATHEMATICAL MODELS), DIGITAL COMPUTERS, COMPUTER LOGIC, SHIFT REGISTERS, FAILURE(ELECTRONICS), MAINTENANCE, BULGARIA.
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE