Accession Number : ADA019810
Title : Performance Evaluation of the CCD450 Digital Memory.
Descriptive Note : Master's thesis,
Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OHIO SCHOOL OF ENGINEERING
Personal Author(s) : Beaumont,James
Report Date : DEC 1975
Pagination or Media Count : 83
Abstract : The Fairchild CCD450 9216-Bit CCD Digital Memory was dynamically tested using the Macrodata MD-100 Memory Exerciser. The MD-100 Memory Exerciser is a high-speed automatic unit designed to test semiconductor memories. An interface circuit was designed and built to enable the CCD450 to be tested on the MD-100. This interface circuit consists of five main sections: a two-phase clock generator, a clock driver unit, a buffer-comparator section, a data strobe pulse generator, and power supply sequencing circuits. The power dissipation, temperature range, and data rate limitations were experimentally determined and compared with the manufacturer's specifications. Operating margins were also obtained for four different CCD450 devices. The resulting Shmoo Plots were then compared with the specified operating ranges of the devices to determine if the devices were performing within the desired limits. A few differences were noted but most of the data compared favorably with the manufacturer's specifications.
Descriptors : *Memory devices, Charge coupled devices, Digital systems, Performance tests, Shift registers, Test equipment, Theses
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE