Accession Number : ADA020136

Title :   Design of Fail-Safe Asynchronous Sequential Machines.

Descriptive Note : Technical rept.,

Corporate Author : ILLINOIS UNIV AT URBANA-CHAMPAIGN COORDINATED SCIENCE LAB

Personal Author(s) : Fan,Yu-Dar

Report Date : JAN 1976

Pagination or Media Count : 88

Abstract : Fail-safe designs are commonly classified as 0-fail-safe or 1-fail-safe designs, where the indicated binary signal is considered the 'safe' value and is produced in case of failures, and N-fail-safe designs, where both of the signals 0 and 1 are considered reliable and a distinct third symbol, N, is produced in case of failures in the circuit. Two methods for the fail-safe design of asynchronous sequential machines are presented in this paper: in the first method, ordinary binary logic elements are used in the realization. Signals are duplicated to guarantee the safe value of the output in the 0-fail-safe or 1-fail-safe case, and a new state assignment method is used in the N-fail-safe case. In the second method, complete sets of 'fail-safe logic elements' are designed first and then assembled into fail-safe realizations. For the N-fail-safe case, two approaches are discussed: one uses three-valued logic, the other uses a binary encoding. The appropriate checking circuits are also designed so that faults are indicated before the capabilities of the designs are exceeded.

Descriptors :   *CENTRAL PROCESSING UNITS, *COMPUTER PROGRAMMING, *FAIL SAFE, LOGIC CIRCUITS, GATES(CIRCUITS), COMPUTER PROGRAMS, ASYNCHRONOUS SYSTEMS, THESES

Subject Categories : Computer Programming and Software
      Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE