Accession Number : ADA115616
Title : The Design and Implementation of a Data Flow Multiprocessor.
Descriptive Note : Master's thesis,
Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
Personal Author(s) : Bray,Michael W
PDF Url : ADA115616
Report Date : Dec 1981
Pagination or Media Count : 157
Abstract : This report presents a data flow multiprocessor designed and implemented with standard laboratory microcomputer boards. Intel SBC 80/20 small board computers were used since their design supported a multibus structure required for multiprocessing. Current data flow techniques were researched in order to find a technique that could be implemented through software. A packet communication architecture was chosen for implementation since other data flow techniques required specialized hardware. The requirements of the multiprocessor were defined using structured analysis techniques. these requirements were then translated into structured modulas. The software modules were then implemented and tested in a top down approach. The data flow multiprocessor software was tested by executing complete data flow programs. The results of the tests demonstrated the functionality of the multiprocessor. However, the multiprocessor software was limited in some respects. The memory allocated for the storage of data flow programs limited the maximum number of data flow instructions that could be represented to only 128. The mathematical operations were also limited in that only 8 bit computations were allowed.
Descriptors : *Multiprocessors, *Data processing, Microcomputers, Data rate, Computer architecture, Computations, Packets, Interfaces, Nodes, Requirements, Cost effectiveness, Microcomputers, Theses
Subject Categories : Computer Hardware
Distribution Statement : APPROVED FOR PUBLIC RELEASE