Accession Number : ADA119116

Title :   The Configurable, Highly Parallel (CHiP) Approach for Signal Processing Applications.

Descriptive Note : Technical rept.,

Corporate Author : PURDUE UNIV LAFAYETTE IN DEPT OF COMPUTER SCIENCES

Personal Author(s) : Snyder,Lawrence

PDF Url : ADA119116

Report Date : May 1982

Pagination or Media Count : 20

Abstract : A VLSI design methodology, built around the CHiP architecture, is described. The switch lattice of the CHiP architecture is the primary design abstraction. The lattice is a flexible design medium with constraints that mirror those of raw silicon. An eight point pipelined Fast Fourier Transform design, used as a running example, is of independent interest for its locally connected layout. (Author)

Descriptors :   *Signal processing, *Computer architecture, *Computer aided design, *Integrated circuits, Algorithms, Fast fourier transforms, Switching circuits, Methodology, Lattice dynamics, Global, Parameters

Subject Categories : Electrical and Electronic Equipment
      Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE