Accession Number : ADA132521

Title :   Optimization Techniques for IC Layout and Compaction,

Corporate Author : ROCHESTER UNIV NY DEPT OF COMPUTER SCIENCE

Personal Author(s) : Kedem,Gershon ; Watanabe,Hiroyuki

PDF Url : ADA132521

Report Date : Sep 1982

Pagination or Media Count : 20

Abstract : This paper describes a new approach for IC layout and compaction. The compaction problem is translated into a mixed integer-linear programming problem of a very special form. A graph based optimization algorithm is used to solve the resulting problem. An experimental program that uses the above techniques is described. The program could be used either as an aid to hand layout or as the bottom part of an automatic layout generation program. (Author)

Descriptors :   *Integrated circuits, Circuit analysis, Logic circuits, Compacting, Computer aided design, Algorithms, Linear programming, Optimization

Subject Categories : Electrical and Electronic Equipment
      Theoretical Mathematics

Distribution Statement : APPROVED FOR PUBLIC RELEASE