Accession Number : ADA132536

Title :   Wafer-Scale Integration of Systolic Arrays,

Corporate Author : MASSACHUSETTS INST OF TECH CAMBRIDGE LAB FOR COMPUTER SCIENCE

Personal Author(s) : Leighton,Frank Thomson ; Leiserson,Charles E

PDF Url : ADA132536

Report Date : Feb 1983

Pagination or Media Count : 31

Abstract : VLSI technologies are fast developing wafer-scale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating wafer-scale systems 'around' such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NP-complete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of this work to problems in VLSI layout theory, graph theory, fault-tolerant systems and planar geometry.

Descriptors :   *Wafers, *Circuit interconnections, *Electric wire, *Silicon, *Chips(Electronics), Arrays, Planar structures, Graphs, Microprocessors, Probability, Tolerance, Failure, Packaging, Performance(Engineering), Nodes, Work, Wire, Models, Losses, Theory, Geometry, Time, Networks, Length, Faults, Cells

Subject Categories : Electrical and Electronic Equipment
      Solid State Physics

Distribution Statement : APPROVED FOR PUBLIC RELEASE