Accession Number : ADA135899

Title :   LSI (Large Scale Integrated) Design for Testability. Final Report of Design, Demonstration, and Testability Analysis.

Descriptive Note : Rept. for 5 Jul 79-15 Dec 80,

Corporate Author : IBM FEDERAL SYSTEMS DIV MANASSAS VA

Personal Author(s) : Groves,R D ; Schoenike,R L

PDF Url : ADA135899

Report Date : Nov 1983

Pagination or Media Count : 301

Abstract : The objective of this effort was to demonstrate IBM Level Sensitive Scan Design methodology as an approach for improving the testability of military LSI/VLSI circuits. LSSD was demonstrated in an LSI component AP101C test bed to be a viable and attractive design approach for military LSI/VLSI components. (Author)

Descriptors :   *Systems engineering, *Test beds, *Integrated circuits, Military applications, Gates(Circuits), Life cycle costs, Requirements, Computer aided design, Logic circuits, Data bases, Flow charting, Schematic diagrams

Subject Categories : Administration and Management
      Electrical and Electronic Equipment
      Test Facilities, Equipment and Methods

Distribution Statement : APPROVED FOR PUBLIC RELEASE