Accession Number : ADA136194

Title :   A Systolic Design Rule Checker.

Descriptive Note : Technical rept.,

Corporate Author : MINNESOTA UNIV MINNEAPOLIS DEPT OF COMPUTER SCIENCE

Personal Author(s) : Kane,R ; Sahni,S

PDF Url : ADA136194

Report Date : Jul 1983

Pagination or Media Count : 31

Abstract : The authors develop a systolic design rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design rule check phase of chip design. (Author)

Descriptors :   *Algorithms, *Computer aided design, *Chips(Electronics), Fabrication, Computer architecture, Polygons, Errors, Edges

Subject Categories : Electrical and Electronic Equipment
      Theoretical Mathematics
      Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE