Accession Number : ADA138466

Title :   PLAFST Programmable Logic Array from State Table.

Descriptive Note : Master's thesis,

Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING

Personal Author(s) : Pelan,D C

PDF Url : ADA138466

Report Date : Dec 1983

Pagination or Media Count : 140

Abstract : Programmable Logic Array From State Table (PLAFST) is a computer aided design tool that takes a symbolic state table as input and produces a very large scale integrated (VLSI) circuit implementation of the symbolic state table. The state table is first reduced symbolically using equivalence partitioning. A near optimal binary state assignment is made based on the Story, Harrison, and Reinhard procedure as modified by Noe and Ryhne. Distinct state assignment variables are sorted based on cost estimates obtained by increasing the number of adjacencies in the state transition table. Once sorted, the actual costs of valid state assignments made from the state variables are calculated. Since state assignments with the lowest cost estimates are investigated first, and optimal solution is found with a small number of iterations. This binary state assignment is demonstratably less costly than either simple or gray code assignments of the state variables. The VLSI circuit consists of a programmable logic array and clocked buffers. The state buffers are properly interconnected. The final outputs are Chip Layout Language and Caltech Intermediate Format descriptions of the integrated circuit. PLAFST also plots the final integrated circuit. (Author)

Descriptors :   *Computer aided design, *Computer programs, *Integrated circuits, Requirements, Computer files, Buffers, Circuit interconnections, Arrays, Logic circuits, Theses

Subject Categories : Electrical and Electronic Equipment
      Computer Programming and Software

Distribution Statement : APPROVED FOR PUBLIC RELEASE