Accession Number : ADA181572

Title :   On-Chip Instruction Caches for High Performance Processors,

Corporate Author : STANFORD UNIV CA COMPUTER SYSTEMS LAB

Personal Author(s) : Agarwal,Anant ; Chow,Paul ; Horowitz,Mark ; Acken,John ; Salz,Arturo

PDF Url : ADA181572

Report Date : Jan 1987

Pagination or Media Count : 12

Abstract : Continued increases in clock rates of VLSI processors demand a reduction in the frequency of expensive off-chip memory references. Without such a reduction, the chip crossing time and the constraints of external logic will severely impact the clock cycle. By absorbing a large fraction of instruction references, on-chip caches substantially reduce off-chip communication. Minimizing the average instruction access time with a limited silicon budget requires careful analysis of both cache architecture and implementation. This paper examines some important design issues and tradeoffs that maximize the performance of on-chip instruction caches, while retaining implementation ease. Our discussion focuses on the instruction cache design for MIPS-X, a pipelined, 32-bit, reduced instruction set, 20 MIPS peak, CMOS processor designed at Stanford. The on-chip instruction cache is 2K bytes and allows single-cycle instruction accesses. Trace driven simulations show that the cache has an average miss rate of 12 percent resulting in an average instruction access time of 1.24 cycles. Reprints.

Descriptors :   *ARCHITECTURE, *INSTRUCTIONS, *CHIPS(ELECTRONICS), *CLOCKS, *ACCESS TIME, CYCLES, EXTERNAL, LOGIC, CROSSINGS, TIME, RATES, LEARNING, BUDGETS, SILICON, REDUCTION, REPRINTS

Subject Categories : Computer Systems

Distribution Statement : APPROVED FOR PUBLIC RELEASE