Accession Number : ADA182460

Title :   Generating Incremental VLSI Compaction Spacing Constraints,

Corporate Author : STANFORD UNIV CA

Personal Author(s) : Carpenter,Clyde W ; Horowitz,Mark

PDF Url : ADA182460

Report Date : Jan 1986

Pagination or Media Count : 7

Abstract : This paper describes using adjacency lists to incrementally generate design rule spacing constraints. The algorithm generates the smallest complete set of constraints for a design, yielding fast compaction, and is as fast or faster than ordinary constraint generation methods even when the incremental features are not used. The adjacency list data structure allows one to very quickly move, insert or delete objects and generate an updated set of constraints.

Descriptors :   *ALGORITHMS, *COMPACTING

Subject Categories : Electrical and Electronic Equipment
      Computer Programming and Software

Distribution Statement : APPROVED FOR PUBLIC RELEASE