Accession Number : ADA182869
Title : Rule-Based Circuit Optimization for CMOS VLSI.
Descriptive Note : Technical rept.,
Corporate Author : ILLINOIS UNIV AT URBANA COORDINATED SCIENCE LAB
Personal Author(s) : Lai,Feipei
PDF Url : ADA182869
Report Date : Jul 1987
Pagination or Media Count : 119
Abstract : A closed-loop design system, iJADE, has been developed in Franz LISP. iJADE is a hierarchical CMOS VLSI circuit optimizer. Using a switch-level timing simulator and a timing analyzer, the program pinpoints the critical paths. The path delay reduction algorithms and a rule-based expert system are then applied to adjust transistor sizes such that the speed of the circuit can be improved while keeping constraints satisfied. iJADE is also capable of detecting and correcting the timing errors of synchronous circuits. The circuit is described in SPICE-like input format and then partitioned into blocks. Delays are computed on a block-by-block basis hierarchically, using a simple model based on input rise time, block type, and output load. Keywords include: Circuit optimization, CMOS, VLSI, and iJADE.
Descriptors : *CRITICAL PATH METHODS, *ALGORITHMS, *ANALYZERS, *TRANSISTORS, *CLOSED LOOP SYSTEMS, *CIRCUITS, OPTIMIZATION, PATHS, REDUCTION, TIME, SIZES(DIMENSIONS), OUTPUT, ERRORS
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE