Accession Number : ADA184486

Title :   Integrated Circuit Design.

Descriptive Note : Final rept. Dec 83-Apr 84,

Corporate Author : HUGHES RESEARCH LABS MALIBU CA

Personal Author(s) : Wong,V S ; Gringberg,J

PDF Url : ADA184486

Report Date : Jun 1987

Pagination or Media Count : 62

Abstract : This report describes the results of a study on the chip design of a low-power filter, using state-of-the-art CMOS technology. The filter is for speech applications and is specified to have 1024 type with programmable weights and linear phase. The chip implementation is to have a word length of 8 to 12 bits and consume a maximum of 2.0 mA at 3.6V. Included are current capabilities of CMOS/SOS/bulk, technology, and in particular, the Hughes VHSIC CMOS process. The architecture of the filter is discussed and estimates are made for the power consumption, speed, device count, and projected chip size of the filter implementation. A comparison of a multiple tape and a single tape implementation of the filter is also presented in terms of power consumption and operational speed.

Descriptors :   *INTEGRATED CIRCUITS, *COMPLEMENTARY METAL OXIDE SEMICONDUCTORS, *SILICON, SAPPHIRE, SUBSTRATES, DIGITAL FILTERS, CHIPS(ELECTRONICS)

Subject Categories : Electrical and Electronic Equipment
      Solid State Physics

Distribution Statement : APPROVED FOR PUBLIC RELEASE