Accession Number : ADA184643
Title : A Digit Pipelined Dynamic Time Warp Processor.
Descriptive Note : Technical rept.,
Corporate Author : PENNSYLVANIA STATE UNIV UNIVERSITY PARK DEPT OF COMPUTER SCIENCE
Personal Author(s) : Irwin,Mary J
PDF Url : ADA184643
Report Date : Aug 1986
Pagination or Media Count : 26
Abstract : A custom CMOS VLSI processor is presented which can achieve real-time isolated word recognition for dictionaries of up to 2000 words. The processor is based on the dynamic time warping (DTW) algorithm, an exhaustive search technique which permits nonlinear pattern matching between an unknown utterance and a reference word. Our design differs from previous DTW designs in that (1) all data is represented in signed-digit, base 4 format; (2) digits are passed between processing elements in a most significant digit first, digit serial fashion; and (3) the algorithms are pipelined at the digit level. Because of these features, nine processing elements will fit on one chip using 3 micron feature size devices and an 84 pin package. The VLSI DTW processor presented is both flexible and modular. The design is independent of the number of coefficients per frame and the precision of those coefficients. The design is also easily expandable in the number frames per word and the warp factor used to achieve the nonlinear matching.
Descriptors : *DIGITAL COMPUTERS, *INTEGRATED CIRCUITS, *COMPLEMENTARY METAL OXIDE SEMICONDUCTORS, *SPEECH RECOGNITION, ISOLATION, ALGORITHMS, TIME
Subject Categories : Computer Hardware
Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE