Accession Number : ADA185032

Title :   An Extension to the Multilevel Logic Simulator for Microcomputers.

Descriptive Note : Master's thesis,

Corporate Author : NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s) : Albuquerque, Julio C De

PDF Url : ADA185032

Report Date : Jun 1987

Pagination or Media Count : 256

Abstract : One of the most time consuming parts of the design process is the debugging of the project. This happens when simple modifications to a circuit require recompilation of the whole circuit. In the CAD tool currently available for digital systems design, compilation is a bottle neck. The VOHL system has an extremely efficient simulator phase and a reasonable but slower compilation phase. This thesis investigates a mechanism for eliminating the need to recompile the complete circuit when small changes are needed.

Descriptors :   *DIGITAL SIMULATION, *DEBUGGING(COMPUTERS), *CIRCUIT TESTERS, COMPUTER AIDED DESIGN, COMPILERS, EDITING, SYNTAX, THESES, GATES(CIRCUITS), INTEGRATED CIRCUITS, COMPUTER PROGRAMS

Subject Categories : Computer Programming and Software
      Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE