Accession Number : ADA187493

Title :   RELIC: A Reliability Simulator for Integrated Circuits,

Corporate Author : MASSACHUSETTS INST OF TECH CAMBRIDGE RESEARCH LAB OF ELECTRONICS

Personal Author(s) : Hohol, Teresa S ; Glasser, Lance A

PDF Url : ADA187493

Report Date : Jan 1987

Pagination or Media Count : 8

Abstract : Many of the failure mechanisms which cause reliability problems in VLSI chips can be influenced or avoided in the circuit design phase. RELIC is a reliability simulator developed to analyze and predict the stress and wear on MOS VLSI chips due to such mechanisms. RELIC uses a simple methodology for abstracting the idea of the stress from any particular failure mechanism, thus allowing analyses of many different failure mechanisms. There are currently three failure mechanisms analyzed by RELIC: metal migration, hot-electron trapping, and time-dependent dielectric breakdown (TDDB).

Descriptors :   *BREAKDOWN(ELECTRONIC THRESHOLD), *DIELECTRIC PROPERTIES, *FAILURE, *INTEGRATED CIRCUITS, *SIMULATORS, FAILURE(MECHANICS), METALS, METHODOLOGY, MIGRATION, PHASE SHIFT CIRCUITS, RELIABILITY, TIME DEPENDENCE

Subject Categories : Electrical and Electronic Equipment
      Electricity and Magnetism

Distribution Statement : APPROVED FOR PUBLIC RELEASE