Accession Number : ADA188553
Title : A Methodology for Hardware Verification Based on Logic Simulation.
Descriptive Note : Interim rept.,
Corporate Author : CARNEGIE-MELLON UNIV PITTSBURGH PA DEPT OF COMPUTER SCIENCE
Personal Author(s) : Bryant, Randal E
PDF Url : ADA188553
Report Date : Dec 1987
Pagination or Media Count : 16
Abstract : A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system specification will produce particular response to a sequence of simulation commands. This style of verification has advantages over other proof methods in being readily automated and requiring less attention to the low level details of the design. It has advantages over other approaches to simulation in providing more reliable results, often at a comparable cost. This paper presents the theoretical foundations of several related approaches to circuit verification based on logic simulation. These approaches exploit the three valued modeling capability found in most logic simulators, where the third value x indicates a signal with unknown digital value. Although the circuit verification problem is NP-hard as measured in th size of the circuit description, several techniques can reduce the simulation complexity to a manageable level for many practical circuits. Keywords: Digital circuits; Computations; Verifiers; Random access memory.
Descriptors : *CIRCUITS, *DIGITAL SYSTEMS, *LOGIC DEVICES, *SIMULATION, COMPUTATIONS, COSTS, LOGIC, LOW LEVEL, MODELS, RANDOM ACCESS COMPUTER STORAGE, RELIABILITY, SIMULATORS, SPECIFICATIONS, THEORY
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE