Accession Number : ADA189942

Title :   An Analysis of Multiple Grain CHiP Architectures.

Descriptive Note : Final rept. 15 Apr 85-30 Sep 86,

Corporate Author : WASHINGTON UNIV SEATTLE DEPT OF COMPUTER SCIENCE

Personal Author(s) : Snyder, Lawrence

PDF Url : ADA189942

Report Date : 28 Feb 1987

Pagination or Media Count : 11

Abstract : The major accomplishments of the Blue CHiP Project Multigrain Architecture Research and described in the areas of theory, algorithms, architecture software and VLSI. A multigauge architecture is a design for a standard von Neumann machine that permits the data path to be partitioned into subunits that can execute concurrently when the data values are small . Thus it is a method of achieving parallelism within the arithmetic/logic unit of a computer that is applicable to both stand alone serial processors and to the processor elements of highly parallel computers. Its advantages are the twin benefits of parallelism for narrow data and the ability to use the processor in its regular mode under programmer control when full precision is necessary. There is the aded benefit that multiguaging is available with minimal added hardware in certain cases, (explained below) but this is simply a benefit, not the justification for the architecture. Keywords: Parallel computation, Multigauge architecture, Parallelism, Quarter Horse multiprocessor, SIMD, MIMD, Poker programming environment, CHiP architectures, Retargeting, Hearts Systolic array.

Descriptors :   *ARITHMETIC UNITS, *COMPUTER ARCHITECTURE, *COMPUTER PROGRAMMING, *MULTIPROCESSORS, *PROCESSING EQUIPMENT, *SERIAL PROCESSORS, ALGORITHMS, BENEFITS, COMPUTATIONS, COMPUTERS, DATA TRANSMISSION SYSTEMS, HORSES, LOGIC DEVICES, PARALLEL ORIENTATION, PATHS, TARGETING, THEORY

Subject Categories : Computer Hardware
      Computer Programming and Software

Distribution Statement : APPROVED FOR PUBLIC RELEASE