Accession Number : ADA190483
Title : Design and Implementation of VLSI Prime Factor Algorithm Processor.
Descriptive Note : Master's thesis,
Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
Personal Author(s) : Hauser, Robert S
PDF Url : ADA190483
Report Date : Dec 1987
Pagination or Media Count : 168
Abstract : High-speed digital signal processing has a wide range of applications including, radar, sonar, image processing, and target acquisition. The calculations of the Discrete Fourier Transform (DFT) used in these applications has long been a significant bottleneck for high-speed processing. Previous AFIT students have adopted a Prime Factor Algorithm (PFA) method using Winogard Fourier Transform (WFT) processors. Three WFT processors are pipelined into a system capable of computing a 4080-point DFT on complex data approximately every 120 microseconds when operating with a 70 MHz clock. This thesis effort addressed the design and implementation of PFA controller chip and interconnecting memory modules between the WFT processors. The PFA controller is an application specific processor to control the flow of information in the pipeline, interface to the WFT processors, monitor pipeline status, and take corrective action in the presence of faults. the interconnecting memory modules buffer the data coming out of a WFT processor and going into another allowing concurrent reading and writing.
Descriptors : *ALGORITHMS, *CHIPS(ELECTRONICS), *DIGITAL SYSTEMS, *DISCRETE FOURIER TRANSFORMS, *IMAGE PROCESSING, *PROCESSING EQUIPMENT, *SIGNAL PROCESSING, CONTROL, FOURIER TRANSFORMATION, HIGH RATE, INFORMATION TRANSFER, PROCESSING, RADAR, SONAR, STUDENTS, TARGET ACQUISITION, THESES
Subject Categories : Computer Hardware
Electrical and Electronic Equipment
Computer Programming and Software
Distribution Statement : APPROVED FOR PUBLIC RELEASE