Accession Number : ADA190519
Title : Fabrication and Electrical Characterization of Multilevel Aluminum Interconnects Used to Achieve Silicon-Hybrid Wafer-Scale Integration.
Descriptive Note : Master's thesis,
Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING
Personal Author(s) : Takahashi, Grant L
PDF Url : ADA190519
Report Date : Dec 1987
Pagination or Media Count : 182
Abstract : The purpose of this research was to develop, fabricate, and electrically characterize a wafer-scale process developed for use with the 272-point Prime Factor Algorithm (PFA) processor. This process integrates discrete integrated circuit die in a planarized wafer package. The entire wafer surface was coated with photosensitive polyimide, which was patterned with vias for the interconnect contacts. The two die were electrically interconnected with printed aluminum interconnects using conventional silicon processing equipment. The original goals of this research included a system test to evaluate the interconnect network. However, difficulties in the processing environment only allowed a single interconnect to be parametrically evaluated up to 10 MHz. The aluminum interconnect was 26 microns wide and 1.2 microns thick. This interconnect exhibited no distinguishable propagation delay and attenuation for a one centimeter path length.
Descriptors : *ALUMINUM, *DIES, *INTEGRATED CIRCUITS, *PATHS, *PRINTED CIRCUITS, *PROCESSING EQUIPMENT, *WAFERS, CIRCUITS, CONNECTORS, DELAY, DISCRETE DISTRIBUTION, LENGTH, PHOTOSENSITIVITY, POLYIMIDE RESINS, PROCESSING, PROPAGATION, SILICON, SURFACES, THESES
Subject Categories : Electrical and Electronic Equipment
Solid State Physics
Distribution Statement : APPROVED FOR PUBLIC RELEASE