Accession Number : ADA195150

Title :   Fast On-Chip Delay Estimation for Cell-Based Emitter Coupled Logic,

Corporate Author : MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER

Personal Author(s) : O'Brien, Peter R ; Wyatt, John L , Jr ; Savarino, Thomas L ; Pierce, James M

PDF Url : ADA195150

Report Date : Feb 1988

Pagination or Media Count : 6

Abstract : The goal of this work is to produce fast, but accurate, estimates of best and worst case delay for on-chip emitter coupled logic (ECL) nets. The work consists of two major parts: (1) macromodelling of ECL logic gates acting as both sources and loads; and (2) delay estimation for individual nets using the gate macromodel parameters and RC tree models for metal interconnect. Both of the above functions (gate macromodeling and delay estimation) have been extensively tested on an industrial ECL process and cell (i.e., logic gate) library. The success of a macromodelling approach relies on repetitive use of members of a library of modelled cells. A fixed computational cost (several c.p.u. hours per cell) is paid to obtain simplified macromodel parameter values. Resultant timing estimates are typically within 5-10% of SPICE and are obtained roughly three orders of magnitude more quickly than SPICE.

Descriptors :   *CHIPS(ELECTRONICS), *COUPLING(INTERACTION), *GATES(CIRCUITS), *LOGIC CIRCUITS, COMPUTATIONS, COSTS, DELAY, EMITTERS, ESTIMATES, LOGIC, MODELS, PARAMETERS, TIME, TREES

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE