Accession Number : ADA195431

Title :   Architecture of a Message-Driven Processor,

Corporate Author : MASSACHUSETTS INST OF TECH CAMBRIDGE MICROSYSTEMS RESEARCH CENTER

Personal Author(s) : Dally, W J ; Chao, L ; Chien, A ; Hassoun, S ; Horwat, W

PDF Url : ADA195431

Report Date : Nov 1987

Pagination or Media Count : 10

Abstract : We propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches. Our architecture also includes a novel memory organization that permits both indexed and associative accesses and that incorporates an instruction buffer and message queue. Simulation results suggest that this architecture reduces message reception overhead by more than an order of magnitude.

Descriptors :   *COMPUTER ARCHITECTURE, *INSTRUCTIONS, *NODES, BUFFERS, MEMORY DEVICES, PERFORMANCE(ENGINEERING), PROCESSING, SIMULATION, SWITCHES

Subject Categories : Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE