Accession Number : ADA195993

Title :   A Model for Architectural Comparison.

Descriptive Note : Technical rept.,

Corporate Author : WASHINGTON UNIV SEATTLE DEPT OF COMPUTER SCIENCE

Personal Author(s) : Ho, Sam ; Snyder, Larry

PDF Url : ADA195993

Report Date : Apr 1988

Pagination or Media Count : 17

Abstract : Recently, architectures for sequential computers have become a topic of much discussion and controversy. At the center of this storm is the Reduced Instruction Set Computer, or RISC, first described at Berkeley in 1980. While the merits of the RISC architecture cannot be ignored, its opponents have tried to do just that, while its proponents have expanded and frequently exaggerated them. This state of affairs has persisted to this day. This paper attempts not to settle the controversy, since indeed there likely is no one answer, but to provide a quantitative framework for a rational discussion of the issues. This paper, seeks to shed some light on this topic. The model presented takes an architecture and a computation. It has the following features. (1) Quantitatively measures an architecture; (2) Examines an architecture working on a computation; (3) Separates the overall computation into logical pieces; (4) Determines from the architecture how long each piece takes; (5) Considers how much parallelism is available; and (6) Compares the results with other architectures. (KR)

Descriptors :   *COMPUTER ARCHITECTURE, ARCHITECTURE, COMPARISON, COMPUTERS, INSTRUCTIONS, REDUCTION, SEQUENCES, STORMS

Subject Categories : Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE