Accession Number : ADA196983
Title : Design Definition for a Digital Beamforming Processor.
Descriptive Note : Final rept. Jan-Nov 87,
Corporate Author : TEXAS INSTRUMENTS INC DALLAS DEFENSE SYSTEMS AND ELECTRONICS GROUP
Personal Author(s) : Langston, J L ; Sanzgiri, Shashikant ; Hinman, Karl ; Keisner, Kevin ; Garcia, Domingo
PDF Url : ADA196983
Report Date : Apr 1988
Pagination or Media Count : 133
Abstract : Very large scale integrated circuit technology now makes large bandwidth digital beamforming array antennas practical. Algorithms and architectures were investigated for the implementation of a processor capable of producing large bandwidth multiple output beams for both near and far-term applications. DFT and FFT algorithms in element space and beam space were investigated. Structures for dedicated algorithm execution with highly pipelined, systolic hardware were examined. Arithmetic execution alternatives were considered. The impact of channel errors were investigated and methods of calibrating the beamformer to compensate for these errors were developed. The effects of quantization errors were investigated and processor dynamic range requirements were assessed. The capabilities of Si and GaAs technologies were assessed. The implementation of a processor chip set using Application Specific Integrated Circuits (ASIC) was investigated. A recommended brassboard demonstration system design was derived. Keywords include: Beamforming system; Brassboard system, Very large scale integrated circuit, and Application specific integrated circuits. (RRH).
Descriptors : *CHIPS(ELECTRONICS), *PROCESSING EQUIPMENT, ALGORITHMS, ARITHMETIC, BEAM FORMING, BRASSBOARD MODELS, CHANNELS, DIGITAL SYSTEMS, DYNAMIC RANGE, ERRORS, GALLIUM ARSENIDES, IMPACT, INTEGRATED CIRCUITS, QUANTIZATION, REQUIREMENTS
Subject Categories : Computer Hardware
Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE