Accession Number : ADA215668

Title :   A Circuit Extraction System and Graphical Display for VLSI (Very Large Scale Integrated) Design.

Descriptive Note : Master's thesis,

Corporate Author : AIR FORCE INST OF TECH WRIGHT-PATTERSON AFB OH SCHOOL OF ENGINEERING

Personal Author(s) : Yarost, Stuart A

PDF Url : ADA215668

Report Date : Dec 1989

Pagination or Media Count : 124

Abstract : This thesis proposes a system for higher-order logic extraction of components from a net-list of transistors and the graphical display of the extracted components. Critical sections have been implemented to demonstrate the feasibility of the system. These sections include a prototype expert system written in CLIPS and a graphical display capable of displaying extracted components on a Sun workstation. Extraction techniques which were developed in this effort use pattern matching and multiple passes. Graphical techniques used in the display include simple line drawing and translation of images. This research has the potential to provide savings of time and effort to engineers designing new circuits or reverse-engineering older circuits for which no adequate specifications exist. This system will also help to close the design cycle and allow the designer to assure that what he has physically designed is what he has logically designed. (RRH)

Descriptors :   *CIRCUITS, *COMPUTER PROGRAMS, *DISPLAY SYSTEMS, *ENGINEERING DRAWINGS, *EXTRACTION, *GRAPHICS, *IMAGES, *PATTERNS, FEASIBILITY STUDIES, LINES(GEOMETRY), MATCHING, PROTOTYPES, SAVINGS, STATIONS, SUN, TIME, TRANSLATIONS, WORK

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE