Accession Number : ADA259455
Title : A Coupled Multi-ALU Processing Node for a Highly Parallel Computer.
Descriptive Note : Technical rept.,
Corporate Author : MASSACHUSETTS INST OF TECH CAMBRIDGE ARTIFICIAL INTELLIGENCE LAB
Personal Author(s) : Keckler, Stephen W.
Report Date : SEP 1992
Pagination or Media Count : 166
Abstract : By 1995, improvements in semiconductor technology will allow as many as four high-performance floating-point ALUs and several megabits of memory to reside on a single chip. Multiple arithmetic units can be organized into a single processor to exploit instruction-level parallelism. Processor Coupling is a mechanism for controlling multiple ALUs to exploit both instruction-level and inter-thread parallelism. Processor Coupling employs both compile time and runtime scheduling. The compiler statically schedules individual threads to discover available intra thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle by cycle basis, and several threads can be active concurrently.... Instruction level parallelism, Multithreading, Compile time scheduling, Parallel computers, Runtime scheduling.
Descriptors : *COMPILERS, *PARALLEL PROCESSORS, ARITHMETIC UNITS, COMPUTERS, COUPLINGS, SEMICONDUCTOR DEVICES, THESES.
Subject Categories : Computer Programming and Software
Distribution Statement : APPROVED FOR PUBLIC RELEASE