Accession Number : ADA269148
Title : Synthesis Techniques and Analysis Tool for On-Chip Fault-Tolerance.
Descriptive Note : Final rept.,
Corporate Author : TEXAS A AND M UNIV COLLEGE STATION
Personal Author(s) : Pradham, Dhiraj K.
Report Date : 1993
Pagination or Media Count : 17
Abstract : This report summarizes significant research on a broad range of issues related to fault-tolerant design both at the chip and system level. First discussed is an integrated approach, currently under development for integrating concurrent checking with BIST. The goal here is to generate synthesis tools to develop low cost fault-tolerant VLSI chip design tools that are both easy to test as well as being robust against operational errors. Section 2 reviews REACT, a tool currently under development for fault-tolerant architecture characterization. Finally, Section 3 presents on-going research on the development of novel fault-tolerant architectures.
Descriptors : *FAULT TOLERANT COMPUTING, *COMPUTER ARCHITECTURE, *CHIPS(ELECTRONICS), VERY LARGE SCALE INTEGRATION, SYSTEMS APPROACH, RELIABILITY(ELECTRONICS), REDUNDANT COMPONENTS.
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE