Accession Number : ADA290054

Title :   Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic.

Descriptive Note : Doctoral thesis,

Corporate Author : MASSACHUSETTS INST OF TECH CAMBRIDGE ARTIFICIAL INTELLIGENCE LAB

Personal Author(s) : Younis, Saed G.

PDF Url : ADA290054

Report Date : JUN 1994

Pagination or Media Count : 116

Abstract : The dynamic dissipation of CMOS circuits is becoming a major concern for designers of personal information systems and large computers. Here, we present new CMOS logic families, including Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically, thus having a power consumption that drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The technique in these new families rely on explicitly reversible pipelined logic gates to provide the necessary information needed to recover most of the energy used in the computation. We report results of testing the first fully quasistatic 8x8 multiplier chip (SCRL-l).

Descriptors :   *GATES(CIRCUITS), *COMPLEMENTARY METAL OXIDE SEMICONDUCTORS, TEST AND EVALUATION, COMPUTERS, DYNAMICS, REPORTS, DISSIPATION, CHARGE TRANSFER, LOGIC CIRCUITS, ENERGY CONSUMPTION.

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE