Accession Number : ADA293356

Title :   Analog Preprocessing in a SNS 2 Micrometers Low-Noise CMOS Folding ADC.

Descriptive Note : Master's thesis,

Corporate Author : NAVAL POSTGRADUATE SCHOOL MONTEREY CA

Personal Author(s) : Carr, Richard D.

PDF Url : ADA293356

Report Date : DEC 1994

Pagination or Media Count : 120

Abstract : Significant research in high performance analog-to-digital converters (ADCs) has been directed at retaining part of the high-speed flash ADC architecture, while reducing the total number of comparators in the circuit. The symmetrical number system (SNS) can be used to preprocess the analog input signal, reducing the number of comparators and thus reducing the chip area and power consumption of the ADC. This thesis examines a Very Large Scale Integrated (VLSI) design for a folding circuit for a SNS analog preprocessing architecture in a 9-bit folding ADC with a total of 23 comparators. The analog folding circuit layout uses the Orbit 2 micrometers CMOS N-well double-metal, double-poly low-noise analog process. The effects of Spice level 2 parameter tolerances during fabrication on the operation of the folding circuit are investigated numerically. The frequency response of the circuit is also quantified. An Application Specific Integrated Circuit (ASIC) is designed.

Descriptors :   *SIGNAL PROCESSING, *INTEGRATED CIRCUITS, *ANALOG TO DIGITAL CONVERTERS, *ANALOG SIGNALS, *PREPROCESSING, *LOW NOISE, *COMPARATORS, INPUT, THESES, VERY LARGE SCALE INTEGRATION, CHIPS(ELECTRONICS), SYMMETRY, ARCHITECTURE, ENERGY CONSUMPTION, COMPLEMENTARY METAL OXIDE SEMICONDUCTORS, FREQUENCY RESPONSE, FOLDING, FLASHES.

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE