Accession Number : ADA294272

Title :   Hardware Implementation of a Desktop Supercomputer for High Performance Image Processing.

Descriptive Note : Technical rept. 10 Feb-1 May 95,

Corporate Author : TEXAS A AND M UNIV COLLEGE STATION DEPT OF ELECTRICAL ENGINEERING

Personal Author(s) : Gyvez, Jose P. De

PDF Url : ADA294272

Report Date : 17 MAY 1995

Pagination or Media Count : 23

Abstract : This report presents a CNN monolithic implementation suitable for Very Large Scale Integration. Novel circuit techniques have been investigated, designed and tested for various basic building blocks such as: (1) a transconductance multiplier, (2) a linear resistor based on a multiplier circuit, (3) an OTA based integrator, (4) a hard limiter circuit and (5) YO circuitry based on Switched Capacitor Techniques. The report addresses both circuit design and layout plan issue. It highlights also the trade-offs among different design parameters including power supplies, dynamic range, area and tolerance. The CNN cell consumes approximately 2.5mW of power and occupies around O.25mm2 of area. The IC has been sent for fabrication through MOSIS. Preliminary experimental results of some basic building blocks are encouraging.

Descriptors :   *IMAGE PROCESSING, *SUPERCOMPUTERS, NEURAL NETS, VERY LARGE SCALE INTEGRATION, MODULAR CONSTRUCTION, POWER SUPPLIES, INTEGRATORS, CIRCUITS, SWITCHING, DYNAMIC RANGE, RESISTORS, CAPACITORS, LIMITER CIRCUITS.

Subject Categories : Computer Hardware
      Cybernetics

Distribution Statement : APPROVED FOR PUBLIC RELEASE