Accession Number : ADA294386
Title : Self Stressing Test Structure Cells.
Descriptive Note : Final technical rept. Jun 92-Mar 94,
Corporate Author : UNIVERSITY OF SOUTHERN CALIFORNIA MARINA DEL REY INFORMATION SCIENCES INST
Personal Author(s) : Tyree, Vance C.
PDF Url : ADA294386
Report Date : FEB 1995
Pagination or Media Count : 106
Abstract : This report addresses the work performed to design on chip reliability prognostics for purposes of monitoring fielded integrated circuits for degradation due to the failure mechanisms of oxide breakdown, electromigration, and hot carrier degradation. The self stressing test structure cells are self-contained standard cells that include the test structure, stressing, and monitoring circuitry and a boundary scan interface to be used with the IEEE 1149.1 boundary scan Test Access Port. The cells have been designed to work within the limitations of a CMOS integrated circuit, i.e., no additional power levels are needed, the cell area has been kept as small as possible, the cells may be incorporated independently from active circuitry, and cells will not degrade chip lifetime. The self stressing cells have been shown to function by simulation, but further study to correlate cell degradation to integrated circuit degradation is required. jg
Descriptors : *STRESSES, *CELLS, *CHIPS(ELECTRONICS), *INTEGRATED CIRCUITS, SCANNING, TEST AND EVALUATION, OSCILLATORS, SIMULATION, POWER LEVELS, DEGRADATION, MONITORING, INTERFACES, DIELECTRICS, FAILURE, CHARGE CARRIERS, HIGH ENERGY, BOUNDARIES, RELIABILITY, OXIDES, SELF CONTAINED, CIRCUITS, COMPLEMENTARY METAL OXIDE SEMICONDUCTORS.
Subject Categories : Electrical and Electronic Equipment
Distribution Statement : APPROVED FOR PUBLIC RELEASE